We can see virtual interface as a handle pointing to the interface instance. An “Interface” is a collection of common signals between two entities & the signal direction is governed by the “modports”. In UVM, for this, we utilize the newly introduced SystemVerilog feature called “Virtual Interface”. port based connection of the DUT ports to the TB ports.Ī standard classification of an UVM environment is shown in the figure 1 below:įigure 1: A Standard Classification of an UVM Environment Hence the communication between the DUT and TB can NOT be like the one in traditional Testbenches i.e. In our traditional directed Testbench environments, all the components are “static” in nature & information (data/control) is also exchanged in the form of signals/wire/net at all levels in the DUT as well as TB.īut this is not the case in the latest “Constrained Random Verification Methodology” like UVM where DUT is static (module based) in nature yet Testbench is class (SystemVerilog OOPs) based. How to connect the DUT to the UVM Testbench.?
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